One of the advantages of a USB Type-C connector is that it can be plugged in any orientation. The USB Type-C receptacle is expected to detect the orientation based on the voltages on CC line and use internal mux to route the signals properly. The USB Type-C plug does not have any in-built mechanism to handle the signal routing.
VESA defines different pin assignments on the USB Type-C connector when sending and receiving DisplayPort signaling. Six possible pin assignments are defined for USB Type-C configured to behave as a Display Source (DFP_D) – A, B, C, D, E, or F. Five possible pin assignments are defined for USB Type-C configured to behave as a Display Sink (UFP_D) – A, B, C, D, or E.
- Pin Assignments A, B, C, and D are intended for use with USB Type-C to USB Type-C Cables and with adaptors from USB Type-C to other video standards such as VGA, DVI, HDMI.
- Pin Assignments E and F are intended for use with adaptors from USB Type-C to DisplayPort plugs or receptacles.
For further details, please contact VESA for VESA DisplayPort Alt Mode on USB Type-C Standard
CYPD1120 can support both 4 lane Type-C to DP/mDP (pin assignment E) and Type-C to VGA/HDMI/DVI (pin assignment C). The default programming on the CYPD1120 supports both C and E pin assignments (C+E). VESA compliance requires that
- A USB Type-C to DP/mDP 4 lane display adapter support only E pin configuration and
- A USB Type-C to HDMI/VGA/DVI 4 lane display adapter support only C pin configuration.
Cypress provides FW and configuration files for supporting pin assignments C, E and C+E. Cypress’s EZ-PD Configuration Utility can be used to program parts with the right firmware and configuration settings.
Please refer to KBA203802 for steps on configuring the pin assignment on the USB Type-C connector based on your adapter. All the required firmware, drivers and tools for this upgrade can be found in the related files section in this page.
Please contact firstname.lastname@example.org in case you have any queries.
|Type||Digital audio/video connector|
|Audio signal||Optional; 1–8 channels, 16 or 24-bit linear PCM; 32–192 kHz sampling rate; maximum bitrate 36,864 kbit/s (4,608 kB/s)|
|Video signal||Optional, maximum resolution limited by available bandwidth|
|Cable||3 meters for full bandwidth transmission over passive cable.|
33 meters over active cable.
|Pins||20 pins for external connectors on desktops, notebooks, graphics cards, monitors, etc. and 30/20 pins for internal connections between graphics engines and built-in flat panels.|
|Max. voltage||16.0 V|
|Max. current||0.5 A|
|Bitrate||1.62, 2.7, 5.4, or 8.1 Gbit/s data rate per lane; 1, 2, or 4 lanes; (effective total 5.184, 8.64, 17.28, or 25.92 Gbit/s for 4-lane link); 1 Mbit/s or 720 Mbit/s for the auxiliary channel.|
|External connector (source-side) on PCB|
|Pin 1||ML_Lane 0 (p)[a]||Lane 0 (positive)|
|Pin 3||ML_Lane 0 (n)[a]||Lane 0 (negative)|
|Pin 4||ML_Lane 1 (p)[a]||Lane 1 (positive)|
|Pin 6||ML_Lane 1 (n)[a]||Lane 1 (negative)|
|Pin 7||ML_Lane 2 (p)[a]||Lane 2 (positive)|
|Pin 9||ML_Lane 2 (n)[a]||Lane 2 (negative)|
|Pin 10||ML_Lane 3 (p)[a]||Lane 3 (positive)|
|Pin 12||ML_Lane 3 (n)[a]||Lane 3 (negative)|
|Pin 13||CONFIG1||Connected to ground[b]|
|Pin 14||CONFIG2||Connected to ground[b]|
|Pin 15||AUX CH (p)||Auxiliary channel (positive)|
|Pin 17||AUX CH (n)||Auxiliary channel (negative)|
|Pin 18||Hot plug||Hot plug detect|
|Pin 19||Return||Return for power|
|Pin 20||DP_PWR||Power for connector (3.3 V 500 mA)|
DisplayPort (DP) is a digital display interface developed by a consortium of PC and chip manufacturers and standardized by the Video Electronics Standards Association (VESA). The interface is primarily used to connect a video source to a display device such as a computer monitor, and it can also carry audio, USB, and other forms of data.
DisplayPort was designed to replace VGA, DVI, and FPD-Link. The interface is backward compatible with other interfaces, such as HDMI and DVI, through the use of either active or passive adapters.
DisplayPort is the first display interface to rely on packetized data transmission, a form of digital communication found in technologies such as Ethernet, USB, and PCI Express. It permits the use of internal and external display connections, and unlike legacy standards that transmit a clock signal with each output, the DisplayPort protocol is based on small data packets known as micro packets, which can embed the clock signal within the data stream. This allows for higher resolution using fewer pins. The use of data packets also makes DisplayPort extensible, meaning additional features can be added over time without significant changes to the physical interface.
DisplayPort can be used to transmit audio and video simultaneously, although each is optional and can be transmitted without the other. The video signal path can range from six to sixteen bits per color channel, and the audio path can have up to eight channels of 24-bit, 192 kHz PCM audio that is uncompressed. A bi-directional, half-duplex auxiliary channel carries device management and device control data for the Main Link, such as VESA EDID, MCCS, and DPMS standards. In addition, the interface is capable of carrying bi-directional USB signals.
The DisplayPort uses an LVDS signal protocol that is not compatible with DVI or HDMI. However, dual-mode DisplayPorts are designed to transmit a single-link DVI or HDMI protocol (TMDS) across the interface through the use of an external passive adapter. This adapter enables compatibility mode and converts the signal from 3.3 volts to 5 volts. For analog VGA/YPbPr and dual-link DVI, a powered active adapter is required for compatibility and does not rely on dual mode. Active VGA adapters are powered by the DisplayPort connector directly, while active dual-link DVI adapters typically rely on an external power source such as USB.
1.0 to 1.1
The first version, 1.0, was approved by VESA on 3 May 2006. Version 1.1a was ratified on 2 April 2007.
DisplayPort 1.0–1.1a allow a maximum bandwidth of 10.8 Gbit/s (8.64 Gbit/s data rate) over a standard 4-lane main link. DisplayPort cables up to 2 meters in length are required to support the full 10.8 Gbit/s bandwidth. DisplayPort 1.1 allows devices to implement alternative link layers such as fiber optic, allowing a much longer reach between source and display without signal degradation, although alternative implementations are not standardized. It also includes HDCP in addition to DisplayPort Content Protection (DPCP). The DisplayPort 1.1a specification can be downloaded for free from the VESA website.
DisplayPort version 1.2 was approved on 22 December 2009. The most significant improvement of the new version is the doubling of the effective bandwidth to 17.28 Gbit/s in High Bit Rate 2 (HBR2) mode, which allows increased resolutions, higher refresh rates, and greater color depth. Other improvements include multiple independent video streams (daisy-chain connection with multiple monitors) called Multi-Stream Transport, facilities for stereoscopic 3D, increased AUX channel bandwidth (from 1 Mbit/s to 720 Mbit/s), more color spaces including xvYCC, scRGB and Adobe RGB 1998, and Global Time Code (GTC) for sub 1 µs audio/video synchronisation. Also Apple Inc.'s Mini DisplayPort connector, which is much smaller and designed for laptop computers and other small devices, is compatible with the new standard.
DisplayPort version 1.2a may optionally include VESA's Adaptive Sync.AMD'sFreeSync uses the DisplayPort Adaptive-Sync feature for operation. FreeSync was first demonstrated at CES 2014 on a Toshiba Satellite laptop by making use of the Panel-Self-Refresh (PSR) feature from the Embedded DisplayPort standard, and after a proposal from AMD, VESA later adapted the Panel-Self-Refresh feature for use in standalone displays and added it as an optional feature of the main DisplayPort standard under the name "Adaptive-Sync" in version 1.2a. As it is an optional feature, support for Adaptive-Sync is not required for a display to be DisplayPort 1.2a-compliant.
DisplayPort version 1.3 was approved on 15 September 2014. This standard increases overall transmission bandwidth to 32.4 Gbit/s with the new HBR3 mode featuring 8.1 Gbit/s per lane (up from 5.4 Gbit/s with HBR2 in version 1.2), for a total data throughput of 25.92 Gbit/s after factoring in 8b/10b encoding overhead. This bandwidth is enough for a 4K UHD display (3840 × 2160) at 120 Hz with 24 bit/px RGB color, a 5K display (5120 × 2880) at 60 Hz with 30 bit/px RGB color, or an 8K UHD display (7680 × 4320) at 30 Hz with 24 bit/px RGB color. Using Multi-Stream Transport (MST), a DisplayPort port can drive two 4K UHD (3840 × 2160) displays at 60 Hz, or up to four WQXGA (2560 × 1600) displays at 60 Hz with 24 bit/px RGB color. The new standard includes mandatory Dual-mode for DVI and HDMI adapters, implementing the HDMI 2.0 standard and HDCP 2.2 content protection. The Thunderbolt 3 connection standard was originally to include DisplayPort 1.3 capability, but the final release ended up with only version 1.2. The VESA's Adaptive Sync feature in DisplayPort version 1.3 remains an optional part of the specification.
DisplayPort version 1.4 was published March 1, 2016. No new transmission modes are defined, so HBR3 (32.4 Gbit/s) as introduced in version 1.3 still remains as the highest available mode. DisplayPort 1.4 adds support for Display Stream Compression 1.2 (DSC), Forward Error Correction, HDR10 extension defined in CTA-861.3, including static and dynamic metadata, the Rec. 2020 color space, and extends the maximum number of inline audio channels to 32.
DSC is a "visually lossless" encoding technique with up to a 3:1 compression ratio. Using DSC with HBR3 transmission rates, DisplayPort 1.4 can support 8K UHD (7680 × 4320) at 60 Hz with 30 bit/px RGB color and HDR, or 4K UHD (3840 × 2160) at 120 Hz with 30 bit/px RGB color and HDR. 4K at 60 Hz with 30 bit/px RGB color and HDR can be achieved without the need for DSC. On displays which do not support DSC, the maximum limits are unchanged from DisplayPort 1.3 (4K 120 Hz, 5K 60 Hz, 8K 30 Hz).
According to a roadmap published by VESA in September 2016, a new version of DisplayPort was intended to be launched in "early 2017". It would have improved the link rate from 8.1 to 10.0 Gbit/s, a 24% increase. This would have increased the total bandwidth from 32.4 Gbit/s to 40.0 Gbit/s. It is unclear whether or not the new version would have continued using the 8b/10b scheme for transport encoding like previous versions, but if so, the maximum data rate for video would have been 32.0 Gbit/s.
However, no new version was released in 2017, likely delayed to make further improvements after the HDMI Forum announced in January 2017 that their next standard (HDMI 2.1) would offer up to 48 Gbit/s of bandwidth. According to a press release on the 3rd of January 2018, "VESA is also currently engaged with its members in the development of the next DisplayPort standard generation, with plans to increase the data rate enabled by DisplayPort by two-fold and beyond. VESA plans to publish this update within the next 18 months.". This implies a bandwidth of around 64.8 Gbit/s for the next version of DisplayPort. Assuming 8b/10b encoding, this would give a data rate of 51.84 Gbit/s.
This should allow for uncompressed RGB / YCBCR 4:4:4 video formats as high as:
- 8K (7680 × 4320) @ 60 Hz 8 bpc (24 bit/px) or 50 Hz 10 bpc (30 bit/px)
- 5K (5120 × 2880) @ 120 Hz 8 bpc or 100 Hz 10 bpc
- 4K (3840 × 2160) @ 200 Hz 8 bpc or 180 Hz 10 bpc
Higher resolutions/refresh rates should also be possible through the use of DSC (compression) or chroma subsampling (YCBCR 4:2:2 or 4:2:0). Higher uncompressed formats may also be possible if the new version replaces 8b/10b encoding with a more efficient encoding method.
The DisplayPort connector can have one, two, or four differential data pairs (lanes) in a Main Link, each with a raw bit rate of 1.62 (reduced bit rate), 2.7 (high bit rate), 5.4 (HBR2), or 8.1 Gbit/s (HBR3) per lane (6.48, 10.8, 21.6, or 32.4 Gbit/s for a full 4-lane link) with self-clock running at 162, 270, 540, or 810 MHz. The effective data rates after decoding are 1.296, 2.16, 4.32, or 6.486 Gbit/s per lane (5.184, 8.64, 17.28, or 25.92 Gbit/s for a full 4-lane link), or 80% of the total, since data is 8b/10b encoded so each eight bits of information are encoded with a ten-bit symbol.
- Forward link channel with 1 to 4 lanes; effective data rate 1.296 (reduced bit rate), 2.16 (high bit rate), 4.32 (HBR2), or 6.48 Gbit/s (HBR3) per lane (total 5.184, 8.64, 17.28, or 25.92 Gbit/s for a 4-lane link).
- 8b/10b encoding provides DC-balancing and Embedded Clock within serial channel (10 bit symbols, 20% coding overhead)
- RGB (unspecified) and YCbCr (ITU-RBT.601-5 and BT.709-4) color spaces, 4:4:4, 4:2:2, or 4:2:0 chroma subsampling
- sRGB, Adobe RGB 1998, DCI-P3, RGB XR, scRGB, xvYCC, Y-only, Simple Color Profile (version 1.2)
- Color depth of 6, 8, 10, 12 and 16 bits per color component
- Optional 8-channel audio with sampling rates up to 24 bit 192 kHz, encapsulation of audio compression formats (including Dolby TrueHD and DTS-HD Master Audio from v1.2)
- Bidirectional half-duplex AUX channel, 1 Mbit/s (v1.0) or optional 720 Mbit/s "Fast AUX" (v1.2)
- Stereoscopic 3D formats: frame sequential (v1.1a), field sequential, side-by-side, top-bottom, line interleaved, pixel interleaved and dual interface (v1.2)
- Optional dual-mode facility generates TMDS and clock for single-link DVI/HDMI signaling using a simple passive dongle for signal level conversion.
- Up to 63 video and audio streams with time-division transport multiplexing and hot-plug bandwidth allocation (from version 1.2)
- 128-bit AESDisplayPort Content Protection (DPCP), 56-bit High-bandwidth Digital Content Protection (HDCP) 1.3 from version 1.1 onwards, HDCP 2.2 (128-bit AES) from version 1.3.
- Internal and external connections so that one standard can be used by computer makers reducing costs.
|Data Rate Required (Gbit/s)|
|1280 × 7200||8 bpc (24 bit/px)||60||1.79||1.54||1.45||1.78|
|1920 × 1080||8 bpc (24 bit/px)||60||4.15||3.33||3.20||3.56|
|1920 × 1080||8 bpc (24 bit/px)||120||8.87||6.85||6.59||7.13|
|1920 × 1200||10 bpc (30 bit/px)||60||5.81||4.62||4.45||-|
|2560 × 1440||8 bpc (24 bit/px)||60||9.37||5.80||5.63||-|
|2560 × 1600||10 bpc (30 bit/px)||60||10.46||8.06||7.82||-|
|3840 × 2160||8 bpc (24 bit/px)||30||8.14||6.31||6.18||7.13|
|3840 × 2160||8 bpc (24 bit/px)||60||17.11||12.80||12.54||14.26|
|3840 × 2400||10 bpc (30 bit/px)||60||23.83||17.78||17.42||-|
|5120 × 2880||8 bpc (24 bit/px)||60||30.64||22.52||22.18||-|
|7680 × 4320||8 bpc (24 bit/px)||30||33.63||24.73||24.48||28.51|
|7680 × 4320||8 bpc (24 bit/px)||60||69.43||50.16||49.65||57.02|
Data rates listed are for RGB or YCBCR 4:4:4 pixel format.
Resolution and refresh frequency limits for DisplayPort
|Video Format||DisplayPort Version / Maximum Data Rate|
|8.64 Gbit/s[b]||17.28 Gbit/s[b]||25.92 Gbit/s[b]||25.92 Gbit/s[b]|
|1080p||1920 × 1080||30||1.58 Gbit/s||Yes||Yes||Yes||Yes|
|1440p||2560 × 1440||30||2.78 Gbit/s||Yes||Yes||Yes||Yes|
|4K||3840 × 2160||30||6.18 Gbit/s||Yes||Yes||Yes||Yes|
|5K||5120 × 2880||30||10.94 Gbit/s||No||Yes||Yes||Yes|
|8K||7680 × 4320||30||24.48 Gbit/s||No||4:2:2[c]||Yes||Yes|
Digital Rights Management (DRM)
DisplayPort 1.0 includes optional DPCP (DisplayPort Content Protection) from Philips, which uses 128-bit AES encryption. It also features full authentication and session key establishment (each encryption session is independent). There is an independent revocation system. This portion of the standard is licensed separately. It also adds the ability to verify the proximity of the receiver and transmitter, a technique intended to ensure users are not bypassing the content protection system to send data out to distant, unauthorized users.
DisplayPort 1.1 added optional implementation of industry-standard 56-bit HDCP (High-bandwidth Digital Content Protection) revision 1.3, which requires separate licensing from the Digital Content Protection LLC.
DisplayPort 1.3 supports HDCP 2.2, which is also employed by HDMI 2.0.
|DisplayPort pins||DVI/HDMI mode|
|Main Link Lane 0||TMDS Channel 2|
|Main Link Lane 1||TMDS Channel 1|
|Main Link Lane 2||TMDS Channel 0|
|Main Link Lane 3||TMDS Clock|
|AUX CH+||DDC Clock|
|AUX CH−||DDC Data|
|Hot Plug Detect||Hot Plug Detect|
|Config 1||Cable Adaptor Detect|
|Config 2||CEC(HDMI only)|
Dual-mode DisplayPort (also known as DisplayPort++) allows devices to directly output single-link HDMI and DVI signals using a simple passive adapter that adjusts from the different connector and the lower voltages used by DisplayPort. When a dual-mode transmitter detects that a DVI or HDMI passive adapter is attached, it switches to DVI/HDMI transmission mode which uses the 4-lane main DisplayPort link and the AUX channel link to transmit three TMDS signals, a clock signal and Display Data Channel data/clock. Dual-mode ports are marked with the DP++ logo; most DisplayPort graphics cards, as well as all Thunderbolt ports with mDP connector, support this mode.
In January 2013, a new VESA specification was released called DisplayPort Dual-Mode Standard version 1.1, which brings dual-mode capabilities on par with HDMI 1.4, allowing a TMDS clock rate of up to 300 MHz, 1080p deep color, 4K resolution, and stereoscopic 3D formats. Passive adapters and ports which support the new data rate will be marked "Type 2" and will be backwards compatible with existing "Type 1" ports.
In September 2014, DisplayPort 1.3 specification was released, which includes mandatory Dual-mode support for HDMI 2.0 protocol, allowing 14.4 Gbit/s of bandwidth and 600 MHz pixel clock, and High-bandwidth Digital Content Protection 2.2.
A notable limitation of dual-mode is that it can only transmit single-link DVI (and HDMI), as the number of pins in the DisplayPort connector is insufficient for dual-link connections. As a result, an active converter is needed for Dual-Link DVI and analog component video such as VGA. Some of these active adapters can rely on the +3.3 V wire in the DisplayPort connector for the conversion, but other types of active conversion, such as Dual-Link DVI, require external power that is often pulled from an available USB port.
VESA anticipates that HDMI and DVI conversion will eventually be handled by active adapters which act as DisplayPort Sink devices. This will make it easier to allow for updates to the latest HDMI and DisplayPort protocols, including dual-link HDMI and dual-link DVI. The benefit also takes into account DisplayPort connections with fewer than 4 lanes, different data rates, and multiple DisplayPort streams. USB Type-C connectors with DisplayPort Alternate Mode do not support dual-mode transmission (DP++). 
Multiple displays on single DisplayPort connector
DisplayPort 1.2 added support for Multi-Stream Transport (MST), enabling multiple monitors to be used via a single DisplayPort connector. This function requires either a standalone MST hub (i.e., branch device), or monitors that are capable of daisy-chaining thanks to an embedded branch device. The first MST hub became available in September 2013, enabling up to 3 displays to be connected to a single DisplayPort connector.
Single Stream Transport (SST) was specified in DisplayPort 1.1a for use between a single Source and Sink Device.
VESA, which created the DisplayPort standard, states the standard is royalty free to implement. However, VESA also acknowledges that "MPEG LA is making claims that DisplayPort implementation requires a license and a royalty payment. It is important to note that these are only claims. Whether these claims are relevant will likely be decided in a US court."  A press release by MPEG LA states that a royalty rate of $0.20 per unit should apply to DisplayPort products manufactured or sold in countries that are covered by one or more of the patents in the MPEG LA license pool. As of 1 September 2015, the MPEG LA license includes patents from Hitachi Maxell, Philips, Lattice Semiconductor, Rambus, and Sony.
As of October 2017 there still seems to be no royalty, according to the VESA's official FAQ.
While the standard may be free to implement, VESA requires membership for access to said standards. The minimum cost is presently $5,000.
Advantages over DVI, VGA and FPD-Link
In December 2010, several computer vendors and display makers including Intel, AMD, Dell, Lenovo, Samsung and LG announced they would begin phasing out FPD-Link, VGA, and DVI-I over the next few years, replacing them with DisplayPort and HDMI. One notable exception to the list of manufacturers is Nvidia, who has yet to announce any plans regarding future implementation of legacy interfaces.
DisplayPort has several advantages over VGA, DVI, and FPD-Link.
- Open standard available to all VESA members[dubious– discuss] with an extensible standard to help broad adoption
- Fewer lanes with embedded self-clock, reduced EMI with data scrambling and spread spectrum mode
- Based on a micro-packet protocol
- Allows easy expansion of the standard with multiple data types
- Flexible allocation of available bandwidth between audio and video
- Multiple video streams over single physical connection (version 1.2)
- Long-distance transmission over alternative physical media such as optical fiber (version 1.1a)
- High-resolution displays and multiple displays with a single connection, via a hub or daisy-chaining
- HBR2 mode with 17.28 Gbit/s of effective video bandwidth allows four simultaneous 1080p60 displays (CEA-861 timings), two 2560 × 1600 × 30 bit @ 120 Hz (CVT-R timings), or 4K UHD @ 60 Hz[note 1]
- HBR3 mode with 25.92 Gbit/s of effective video bandwidth, using CVT-R2 timings, allows eight simultaneous 1080p displays (1920 × 1080) @ 60 Hz, stereoscopic4K UHD (3840 × 2160) @ 120 Hz, or 5120 × 2880 @ 60 Hz each using 24 bit RGB, and up to 8K UHD (7680 × 4320) @ 60 Hz using 4:2:0 subsampling
- Designed to work for internal chip-to-chip communication
- Aimed at replacing internal FPD-Link links to display panels with a unified link interface
- Compatible with low-voltage signaling used with sub-micronCMOS fabrication
- Can drive display panels directly, eliminating scaling and control circuits and allowing for cheaper and slimmer displays
- Link training with adjustable amplitude and preemphasis adapts to differing cable lengths and signal quality
- Reduced bandwidth transmission for 15-metre (49 ft) cable, at least 1920 × 1080p @ 60 Hz at 24 bits per pixel
- Full bandwidth transmission for 3 metres (9.8 ft)
- High-speed auxiliary channel for DDC, EDID, MCCS, DPMS, HDCP, adapter identification etc. traffic
- Can be used for transmitting bi-directional USB, touch-panel data, CEC, etc.
- Self-latching connector
Comparison with HDMI
Although DisplayPort has much of the same functionality as HDMI, it is a complementary connection used in different scenarios. A dual-mode DisplayPort port can emit an HDMI signal via a passive adapter.
HDMI charges an annual fee of US$10,000 to each high-volume manufacturer and a per-unit royalty rate of US$0.04 to US$0.15. HDMI Licensing countered the "royalty-free" claim by pointing out that the DisplayPort specification states that companies can charge a royalty rate for DisplayPort implementation. DisplayPort 1.2 has more bandwidth at 21.6 Gbit/s (17.28 Gbit/s with overhead removed) as opposed to HDMI 2.0's 18 Gbit/s (14.4 Gbit/s with overhead removed). DisplayPort 1.3 raises that to 32.4 Gbit/s (25.92 Gbit/s with overhead removed), and HDMI 2.1 raises that up to 48 Gbit/s (42.67 Gbit/s with overhead removed), adding an additional TMDS link in place of clock lane. DisplayPort also has the ability to share this bandwidth with multiple streams of audio and video to separate devices.
DisplayPort in native mode lacks some HDMI features such as Consumer Electronics Control (CEC) commands. The CEC bus allows linking multiple sources with a single display and controlling any of these devices from any remote;. DisplayPort 1.3 added the possibility of transmitting CEC commands over the AUX channel
DisplayPort Multi-Stream Transport also allows connecting two or three devices together but in the opposite, less "consumer"-oriented configuration: simultaneously driving multiple displays from a single output port.
HDMI uses unique Vendor-Specific Block structure, which allows for features such as additional color spaces. However, these features can be defined by CEA EDID extensions.
Figures from IDC show that 5.1% of commercial desktops and 2.1% of commercial notebooks released in 2009 featured DisplayPort. However, they predicted that the figure for commercial desktops would grow to 89.5%, and for commercial notebooks to 95% by 2014.[needs update] The main factor behind this is the phase-out of VGA, and that both Intel and AMD will also stop building products with FPD-Link by 2013. Nearly 70% of LCD monitors sold in August 2014 in the US, UK, Germany, Japan, and China were equipped with HDMI/DisplayPort technology, up 7.5% on the year, according to Digitimes Research.
Main article: Mini DisplayPort
Mini DisplayPort (mDP) is a standard announced by Apple in the fourth quarter of 2008. Shortly after announcing Mini DisplayPort, Apple announced that it would license the connector technology with no fee. The following year, in early 2009, VESA announced that Mini DisplayPort would be included in the upcoming DisplayPort 1.2 specification. On 24 February 2011, Apple and Intel announced Thunderbolt, a successor to Mini DisplayPort which adds support for PCI Express data connections while maintaining backwards compatibility with Mini DisplayPort based peripherals.
Micro DisplayPort will target systems that need ultra-compact connectors, such as phones, tablets and ultra-portable notebook computers. This new standard will be physically smaller than the currently available Mini DisplayPort connectors. The standard was expected to be released by Q2 2014. This project seems aborted to be replaced by DisplayPort Alt Mode for USB Type-C Standard.
Direct Drive Monitor (DDM) 1.0 standard was approved in December 2008. It allows for controller-less monitors where the display panel is directly driven by the DisplayPort signal, although the available resolutions and color depth are limited to two-lane operation.
Display Stream Compression
Display Stream Compression (DSC) uses a visually lossless low-latency algorithm based on delta PCM coding and YCoCg-R color space; it allows increased resolutions and color depths and reduced power consumption.
DSC has been tested to meet the requirements of ISO/IEC 29170-2 Evaluation procedure for nearly lossless coding using various test patterns, noise, subpixel-rendered text (ClearType), UI captures, and photo and video images.
DSC version 1.0 was released on March 10, 2014, but was soon deprecated by DSC version 1.1 released on August 1, 2014. The DSC standard supports up to 3:1 compression ratio with constant or variable bit rate, 4:4:4 chroma subsampling, optional 4:2:2 conversion and 6/8/10/12 bits per color component.
DSC version 1.2 was released on January 27, 2016 and is included with DisplayPort 1.4; version 1.2a was released on January 18, 2017. The update includes native encoding of 4:2:2 and 4:2:0 formats in pixel containers, 14/16 bits per color, and minor modifications to the encoding algorithm.
DSC compression works on a horizontal line of pixels encoded using groups of three consecutive pixels for native 4:4:4 and simple 4:2:2 formats, or six pixels (three compressed containers) for native 4:2:2 and 4:2:0 formats. If RGB encoding is used, it is first converted to reversible YCgCo. Simple conversion from 4:2:2 to 4:4:4 can add missing chroma samples by interpolating neighboring pixels. Each luma component is coded separately using three independent substreams (four substreams in native 4:2:2 mode). Prediction step is performed using one of the three modes: modified median adaptive coding (MMAP) algorithm similar to the one used by JPEG-LS, block prediction (optional for decoders due to high computational complexity, negotiated at DSC handshake), and midpoint prediction. Bit rate control algorithm tracks color flatness and buffer fullness to adjust the quantization bit depth for a pixel group in a way that minimizes compression artifacts while staying within the bitrate limits. Repeating recent pixels can be stored in 32-entry Indexed Color History (ICH) buffer, which can be referenced directly by each group in a slice; this improves compression quality of computer-generated images. Alternatively, prediction residuals are computed and encoded with entropy coding algorithm based on delta size unit-variable length coding (DSU-VLC). Encoded pixel groups are then combined into slices of various height and width; common combinations include 100% or 25% picture width, and 8-, 32-, or 108-line height.
On January 4, 2017, HDMI 2.1 was announced which supports up to 10K resolution and uses DSC 1.2 for video that is higher than 8K resolution with 4:2:0 chroma subsampling.
Embedded DisplayPort (eDP) 1.0 standard was adopted in December 2008. It aims to define a standardized display panel interface for internal connections; e.g., graphics cards to notebook display panels. It has advanced power-saving features including seamless refresh rate switching. Version 1.1 was approved in October 2009 followed by version 1.1a in November 2009. Version 1.2 was approved in May 2010 and includes DisplayPort 1.2 data rates, 120 Hz sequential color monitors, and a new display panel control protocol that works through the AUX channel. Version 1.3 was published in February 2011; it includes a new Panel Self-Refresh (PSR) feature developed to save system power and further extend battery life in portable PC systems. PSR mode allows GPU to enter power saving state in between frame updates by including framebuffer memory in the display panel controller. Version 1.4 was released in February 2013; it reduces power consumption with partial-frame updates in PSR mode, regional backlight control, lower interface voltage, and additional link rates; the auxiliary channel supports multi-touch panel data to accommodate different form factors. Version 1.4a was published in February 2015; it is based on DisplayPort 1.3 and supports HBR3 data rate, Display Stream Compression 1.1, Segmented Panel Displays, and partial updates for Panel Self-Refresh. Version 1.4b was published in October 2015; its protocol refinements and clarifications are intended to enable adoption of eDP 1.4 in production by mid-2016.
Internal DisplayPort (iDP) 1.0 was approved in April 2010. The iDP standard defines an internal link between a digital TV system on a chip controller and the display panel's timing controller. It aims to replace currently used internal FPD-Link lanes with DisplayPort connection. iDP features unique physical interface and protocols, which are not directly compatible with DisplayPort and are not applicable to external connection, however they enable very high resolution and refresh rates while providing simplicity and extensibility. iDP features non-variable 2.7 GHz clock and is nominally rated at 3.24 Gbit/s data rate per lane, with up to sixteen lanes in a bank, resulting in six-fold decrease in wiring requirements over FPD-Link for a 1080p24 signal; other data rates are also possible. iDP was built with simplicity in mind and it doesn't have AUX channel, content protection, or multiple streams; however it does have frame sequential and line interleaved stereo 3D.
Portable Digital Media Interface (PDMI) is an interconnection between docking stations/display devices and portable media players, which includes 2-lane DisplayPort v1.1a connection. It has been ratified in February 2010 as ANSI/CEA-2017-A.
Wireless DisplayPort (wDP) enables DisplayPort 1.2 bandwidth and feature set for cable-free applications operating in 60 GHz radio band; it was announced on November 2010 by WiGig Alliance and VESA as a cooperative effort.
SlimPort, a brand of Analogix products, complies with Mobility DisplayPort, also known as MyDP, which is an industry standard for a mobile audio/video Interface, providing connectivity from mobile devices to external displays and HDTVs. SlimPort implements the transmission of video up to 4K-UltraHD and up to eight channels of audio over the micro-USB connector to an external converter accessory or display device. SlimPort products support seamless connectivity to DisplayPort, HDMI and VGA displays.
- ^Uncompressed 8 bpc (24 bit/px) color depth with RGB or YCBCR 4:4:4 color format and CVT-R2 timing are used to calculate these data rates. Uncompressed data rate for RGB images in bits per second is calculated as bits per pixel × pixels per frame × frames per second. Pixels per frame includes blanking intervals as defined by CVT-R2.
- ^ abcdOnly a portion of DisplayPort's bandwidth is used for carrying video data. DisplayPort uses 8b/10b encoding, which means that 80% of the bits transmitted across the link represent data, and the other 20% is used for encoding purposes. The maximum bandwidth of DisplayPort (10.8, 21.6, or 32.4 Gbit/s) therefore transports video data at a rate of 8.64, 17.28, or 25.92 Gbit/s.
- ^ abcdefghPossible using YCBCR format with either 4:2:2 or 4:2:0 chroma subsampling as noted. 4:2:2 subsampling is only supported by DisplayPort 1.2 and above. 4:2:0 subsampling is only supported by DisplayPort 1.3 and above.
- ^ abcdPossible using Display Stream Compression (DSC), only supported by DisplayPort 1.4